Publications & Presentations

Choo, Chang Y

Publications & Patents (Selected)

鈥淥ptimization of Swim Pose Estimation and Recognition with Data Augmentation,鈥� Proceedings of IEEE Southwest Symposium of Image Analysis and Interpretation, Santa Fe, New Mexico, March 17-19, 2024 (with J.Ouyang and D.Trinh)

鈥淒esign and Analysis of an FPGA-based CNN for Exercise Recognition,鈥� Proceedings of IEEE CTSoc TRON Symposium, Tokyo, Japan, December 6-8, 2023 (with D.Trinh and J.Ouyang)

鈥淧rediction of Metabolic Syndrome based on Non-invasive Measurement Features for Chronic Disease Management,鈥� Proceedings of 8th International Conference on Computer Technology Applications (ICCTA), pp.242-248, May 2022 (with H. Shin, S. Shim, et al.).

鈥淎 Preliminary Result of Food Object Detection using Swin Transformer,鈥� Proceedings of 8th International Conference on Computer Technology Applications (ICCTA), pp.183-187, May 2022 (with D.Jung, S.Shim, et al.).

鈥淩obust Metabolic Syndrome Risk Index Based on Triangular Areal Similarity,鈥� Proceedings of IEEE International Conference on Bioinformatics and Biomedicine (BIBM), pp.2877-2884, 9-12 December 2021 (with H.Shin, S.Shim, et al.).

鈥淐onvergence of ICT and AT (Automotive Technology) in Silicon Valley", invited keynote, 10th International Conference on ICT Convergence, Jeju Island, Oct.16-18, 2019.

鈥淓mbedding Artificial Intelligence (AI) in Edge Devices,鈥� invited keynote, Embedded Processing Workshop, Jeju Island, Korea, Nov. 15-17, 2018. 

鈥淧erformance Evaluation of FPGA-Based Bit-Scaled CNN Architecture,鈥�&苍产蝉辫;Intel HPC Developer Conference, Denver, Colorado, Nov. 11-12, 2017 (with B.J. Kim).

鈥淪GDR: A Simple GPS-Based Disrupt-Tolerant Routing for Vehicular Networks," 8th Intern. Conf. ICT Convergence, Jeju Island, Oct. 18-20, 2017 (with H.Y. Jung).

鈥淔PGA-Based Hardware Accelerator for Feature Extraction in Automatic Speech Recognition,鈥�&苍产蝉辫;Int. J. lnfo. Commun. Converg. Eng. 13(3): 145-151, Sep. 2015 (with Y.U. Chang and I.Y. Moon).

鈥淣ovel Write request handling for Static Wear Leveling in Flash Memory (SSD) Controller,鈥� Int. J. lnfo. Commun. Converg. Eng. 12(3): 181-185, Sep. 2014 (with P. Gajipara and I.Y. Moon).

鈥淔PGA-Based Design of Black Scholes Financial Model for High Performance Trading,鈥�&苍产蝉辫;Int. J. lnfo. Commun. Converg. Eng. 11(3): 190-198, Sep. 2013 (with L. Malhotra and A. Munjal).

鈥淔PGA Design of a Real-Time Edge Enhancing Smoothing Filter,鈥� IS&T/SPIE Electronic Imaging, Burlingame, California, Feb. 3-7, 2013 (with N. Pandya).

鈥淎n FPGA-Based Embedded Wideband Audio Codec System,鈥� 19th international Conference on Field Programmable Logic and Applications, Prague, Czech Republic, Aug. 31-Sep. 2, 2009.  

鈥淒esign of High-Performance Adaptive FIR Filters Using FPGA,鈥� DesignCon, Santa Clara, California, Feb. 4-7, 2008.

鈥淔PGA-Based Hardware Accelerator for Rank and Median Filters for Image processing,鈥�&苍产蝉辫;4th Conference on New Exploratory Technologies, Seoul, Korea, Oct. 25-27, 2007 (with P. Verma).

鈥淔PGA-Based Embedded Acoustic Echo Canceller System,鈥� 4th Conference on New       Exploratory Technologies, Seoul, Korea, Oct. 25-27, 2007 (with W. Zhang).

鈥淓conomic Effects of Indirect Access Regime in the Mobile Telecommunication Market,鈥�&苍产蝉辫;35th Research Conference on Communication, Information and Internet Policy, George MasonUniversitySchool of Law, Arlington, Virginia, Sep. 28-30, 2007 (with B.W. Kim).

 鈥淎n Embedded Adaptive Filtering System on FPGA,鈥� GSPx Conference, Santa Clara, CA, Oct. 30-Nov. 2, 2006 (with P. Padmanabhan, et al.).

鈥淚mplementation of Texas Instruments TMS32010 DSP Processor on Altera FPGA,鈥� GSPx Conference, Santa Clara, CA, September 27-30, 2004 (with J. Chung, et al.).

鈥淢apping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation,鈥� IP Based SOC Design Workshop, Grenoble, France, October 30-31, 2002.

鈥淎 Memory Reduction Scheme for Multi-Channel Echo Canceller Implementation,鈥� Proc. IEEE International Conf. Acoustics, Sound, and Signal Processing, Salt Lake City, Utah, pp.3301-3304, May 7-11, 2001 (with H. Elabd).

鈥淒esigning High-Performance Echo Canceller for VOIP,鈥� DSP Engineering Mag., vol.2, no.1, pp. 12-26, 2000.

鈥淐onstrained Variable-Bit-Rate Control Algorithm for MPEG-2 Encoder,鈥� Proc. SPIE, vol. 3974, pp.133-143, Image and Video Communications and Processing 2000, B. Vasudev; T.R. Hsing; A.G. Tescher; R.L. Stevenson; Eds. (with D. Zhang).

鈥淥ptimization of 2D median filtering algorithm for VLIW architecture,鈥� Proc. SPIE, vol.3970, pp. 70-79, Media Processors 2000, S. Panchanathan; V.M. Bove; S.I. Sudharsanan; Eds. (with M. Tang).

鈥淒esign and Implementation of Digital FIR Filters Using Altera FIR Compiler,鈥� DSP and Multimedia Magazine, 1999.

鈥淰ideo Applications for Distributed Arithmetic,鈥� tutorial workshop paper, ICSPAT-99,  Orlando, Florida, November 1999.

鈥淪yntax-Based Arithmetic Video Coding for Very Low Bitrate Visual Telephony,鈥� Proc. IEEE Intern. Conf. Image Processing, Washington, DC, pp.II410-II413, Oct. 22-25, 1995 (with X. Ran).

鈥淓valuation of Design Parameters for a Cache Vector Quantization System,鈥�&苍产蝉辫; Proc. First IEEE Conference on Image Processing, Austin, Texas, pp. 129-133, Nov. 13-16, 1994 (with N. M. Nasrabadi).

H.26P/TMN2-NSC: National Semiconductor Implementation of ITU H.26P Draft        Recommendation on Video Coding for Narrow Telecommunication Channels at < 64        kbits/s, Confidential Technical Report, Corporate Technology Group, National        Semiconductor, Santa Clara, California, September, 1994 (with X. Ran, et al.).

鈥淒ynamic Finite-State Vector Quantization of Digital Images,鈥� IEEE Transactions on  Communications, vol.42, no.5, pp.2145-2154, May 1994 (with N. M. Nasrabadi and Y.      Feng).

鈥淧erformance Analysis of a Vector Quantizer with Cache Memory,鈥� Proc. 27th Annual  Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp.    956-960, Nov. 1-3, 1993 (with B. A. Cicchetto and N. M. Nasrabadi).

鈥淚nterframe Hierarchical Address-Vector Quantization,鈥� IEEE Journal on Selected Areas in Communications, vol. 10, no. 5, pp. 960-967, June 1992 (with N. M. Nasrabadi and J.U. Roy).

鈥淗opfield Network for Stereo Vision Correspondence,鈥� IEEE Transactions on Neural    Networks, vol. 3, no. 1, pp. 5-13, January 1992 (with N. M. Nasrabadi).

鈥淎 TMS320C25-Based Implementation of Motion-Compensated Interframe Image Coding System,鈥� Proc. First Texas Instruments TMS320 Educators Conference, Houston, Texas, pp. 215-228, July 31 鈥揂ugust 2, 1991 (with N. M. Nasrabadi).

鈥淎 Self-Organizing Adaptive Vector Quantization Technique,鈥� Journal of Visual      Communication and Image Representation, vol. 2, no. 2, pp. 129-137, June 1991 (with N.M. Nasrabadi and Y. Feng).

鈥淎 Multiprocessor System for Interframe Hierarchical Address-Vector Quantization,鈥� Proc. 1991 IEEE International Symposium on Circuits and Systems, Singapore, pp. 61-64, June 11-14, 1991 (with F. J. Desjarlais and N. M. Nasrabadi).

鈥淗ierarchical Block Truncation Coding of Digital HDTV Images,鈥� IEEE Transactions on Consumer Electronics, vol.36, no.3, pp.254-261, August 1990 (with N.M. Nasrabadi, et al.).

鈥淒esign and Analysis of Two-Channel High Definition Television Systems,鈥� IEEE Trans. on Broadcasting, vol. 36, no. 2, pp.175-183, June 1990 (with N.M. Nasrabadi).

 

SELECTED PATENTS:

U.S. Patent No. 9,025,763 (2015) 鈥淎pparatus and Method for cancelling wideband acoustic echo,鈥� (with I.K. Hwang).

U.S. Patent Nos. 7,058,675 (2006) and 7,124,161 (2006) 鈥淎pparatus and method for implementing efficient arithmetic circuits in programmable logic devices,鈥� (with A. Hazanchuk).

U.S. Patent Nos. 5,943,096 (1999) and 6,621,864 (2003) 鈥淢otion vector based frame insertion process for increasing the frame rate of moving images鈥�

U.S. Patent Nos. 5,832,131 (1998) and 5,991,455 (1999) 鈥淗ashing-based vector quantization,鈥� (with X. Ran).

U.S. Patent No. 5,587,710 (1997) 鈥淪yntax based arithmetic coder and decoder,鈥� (with X. Ran, et al.).